1. Field of the Invention
Embodiments of the present invention generally relate to integrated circuit (IC) fabrication methods, and more particularly, to electron beam lithography methods for use in forming patterns in material layers of an IC.
2. Description of the Related Art
In recent years ICs have evolved into complex devices that commonly include millions of transistors, capacitors, resistors, and other electronic components on a single chip. Therefore, there is an inherent demand for increased circuit densities, as well as a continual demand for faster and more efficient circuit components. The combined demands for faster circuits having greater circuit densities imposes corresponding demands on the materials used to fabricate such integrated circuits, as well as on process sequences used for IC fabrication.
For example, in process sequences using conventional photolithographic techniques, a layer of photo-sensitive resist is generally formed over a substrate or stack of material layers on a substrate. An image of a pattern may then be introduced into the photo-sensitive resist layer. Thereafter, the pattern introduced into the photo-sensitive resist layer may be transferred into one or more layers of the material stack formed on the substrate using the layer of photo-sensitive resist as a mask. The pattern may be transferred into a material layer(s) using a chemical and/or physical etchant, which is generally designed to have a greater etch selectivity for the material layer(s) than for the photo-sensitive resist. In other words, the etchant may be designed to etch the material layer(s) at a faster rate than it etches the photo-sensitive resist. The faster etch rate for the one or more material layers of the stack typically prevents the photo-sensitive resist material from being consumed prior to completion of the pattern transfer.
Photolithographic techniques typically introduce the image of the pattern into the photo-sensitive resist layer via a mask in which the pattern is formed. A UV light source placed above the mask irradiates a surface of the layer of photo-sensitive resist with the pattern formed in the mask. Due to limitations in mask formation and associated diffraction effects, however, conventional photolithographic techniques have a lower limit in the dimension of pattern that may be formed. As feature sizes continue to shrink, alternatives to conventional photo-lithographic techniques for forming pattern dimensions below the limits of conventional photolithography are being explored. One such alternative is electron beam (e-beam) lithography.
In general, using e-beam lithography, a pattern is introduced in a layer of electron sensitive resist (e-beam resist) by exposing the resist to a focused e-beam. Rather than utilize a mask to form the patterns, the pattern is typically formed using a raster scan process, during which the e-beam is moved over a surface of the e-beam resist layer and only turned on over designated areas to form the pattern in the e-beam resist. The pattern is then transferred into the e-beam resist during a subsequent development process where either exposed or unexposed portions of the e-beam resist layer are removed depending on whether the e-beam resist is a positive resist or negative resist, respectively. Because e-beam lithography writes a pattern directly into the e-beam resist layer, without the use of a mask, smaller pattern features may be achieved.
Electrons in the e-beam are typically accelerated at voltage levels in a range of 500V to 100 kV. Conventionally, higher accelerating voltages have been associated with greater resolution, possibly due to increased stiffness of the e-beam at higher voltages. However, depending on properties of resist material, at higher accelerating voltages, forward scattering of electrons may occur as the electrons travel through the resist material, which may reduce pattern resolution. Further, backward scattering of the electrons may occur as the electrons reflect off a substrate or other material underlayer, and travel back through the e-beam resist which may also reduce pattern resolution. In an effort to reduce these scattering effects, the acceleration voltage may be lowered (e.g., in a range of 500V to 5 kV), which may also lower the penetration depth of electrons.
The low penetration depth of electrons associated with low voltage e-beam pattern imaging typically necessitates a relatively thin e-beam resist layer which, alone, may have an insufficient etch resistance for use as a mask layer in subsequent pattern transfer etching processes. Therefore, as illustrated in FIG. 1A, a bi-layer resist approach is typically taken, forming a relatively thin e-beam resist layer 106 on top of a thicker mask layer 104. Typically, the thicker mask layer 104 is formed of a non-conductive material, such as a spun-on organic resist material. However, one problem with a non-conductive mask layer 104 is a possible accumulation of electrons at or near a junction of the mask layer 104 and the e-beam resist layer 106.
As illustrated in FIG. 1B, accumulations of electrons may repel electrons from the e-beam, causing the e-beam to lose focus. As illustrated in FIG. 1C, loss of focus in the e-beam may result in a lower resolution pattern with rough sidewalls 110 transferred into the e-beam resist layer 106 during a subsequent development process (a negative resist is illustrated). Consequently, the resolution of a feature formed in the mask layer 104 (e.g., via an etching process) using the e-beam resist layer 106 as a mask may also be lowered.
Accordingly, what is needed is an improved method for forming a pattern in an IC using e-beam lithography.